For example, in Non-Patent Document 1 and Non-Patent Document 2, a phase-change memory with a chalcogenide material as a storage element and a diode as a selecting element is described. As a chalcogenide material, a Ge—Sb—Te group, an Ag—In—Sb—Te group, or the like containing at least antimony (Sb) and tellurium (Te) is used.
FIG. 51 is a drawing of local cell arrays LCA0 to LCAn from a memory core structure described in FIG. 2 of Non-Patent Document 1. Each of the local cell arrays, as typified by the local cell array LCA0, has a structure in which memory cells MC00 to MCnn each having a resistive storage element R and a diode for selection D using a phase-change material serially connected are disposed respectively at points of intersection of (n+1) local bit lines LBL0 to LBLn and (n+1) word lines WL0 to WLn.
The local bit lines LBL0 to LBLn are connected to a global bit line GBL0 via NMOS transistors MNYS0 to MNYSn, respectively, MNYS0 to MNYSn are controlled by local column selection signals LY0 to LYn, respectively, connected to gate electrodes. That is, with one of MNYS0 to MNYSn being activated to conduction, one of LBL0 to LBLn is electrically connected to GBL0. Note that NMOS transistors MND0 to MNDn are respectively inserted between LBL0 to LBLn and a ground voltage VSS. MND0 to MNDn are controlled by a local-bit-line discharge signal LBLDIS connected to each gate electrode.
FIG. 52 is a drawing of blocks selected in a read operation from a circuit block diagram in a read route described in FIG. 6 of Non-Patent Document 2. A selected block BLOCK_i is configured of four input/output blocks IO-block0 to IO-block3. Above and below each input/output block, a circuit controlling a connection between a bit line and a global bit line GBL (a local column decoder) LYDEC is disposed. Also, on the left and right of each input/output block, a section-word-line driving circuit SWD is disposed. To suppress fluctuations of voltage of a word line that is to be at a ground voltage, each section-word-line driving circuit SWD drives the word line extending over the input/output blocks on the left and right. Note that each section-word-line driving circuit SWD is controlled by a common main word line.
Also, FIG. 7 of Patent Document 1 depicts a block structure when a multibank scheme is adopted to a cross-point memory. In this document, a semiconductor storage device having a memory cell array structure in which a memory cell does not include an element for selection other than a storage element, and the storage element is directly connected to a data line (a row selection line) and a bit line (a column selection line) in a memory cell is referred to as a cross-point memory. In particular, in FIG. 7, a variable resistance element is used as a storage element. Also, in the multibank scheme in this document, a small-sized memory cell array is called one memory bank, and a plurality of such memory banks are disposed in a matrix in a row direction and a column direction to achieve a desired memory capacity (the number of memory cells).
In this memory cell array, the number of memory cells that are connected to one data line and one bit line is restricted to any value. In this multibank scheme, main data lines GD as many as the number of data lines of each of banks BKk arranged along a row direction each cross over each bank to extend in a row direction, and are respectively connected to data lines DLi via a bank selection transistor BDk. Also, main bit lines GBLj as many as the number of bit lines of each of the banks arranged along a column direction each cross over each bank to extend in a column direction, and are respectively connected to bit lines BLj via a bank selection transistor BBk. Here, i represents a data line number, j represents a bit line number, and k represents a bank number. Each bank is configured of the same number of main data lines GDLi and data lines DLi and the same number of main bit lines GBLj and bit lines BLj.
In this structure, a predetermined data line voltage supplied from a data line driver 10 connected to the main data line GDLj is supplied to each data line DLi of the selected bank via the main data line GDLi. Also, a predetermined bit line voltage supplied from a bit line driver 20 connected to the main bit line GBLi is supplied to each bit line BLj of the selected bank via the main bit line GBLj. Thus, a desired memory cell can be selected. Also, in the cross-point memory of the multibank scheme, a predetermined voltage is applied to each data line DLi and each bit line BLj of only the selected bank, thereby letting a current flow. Such voltage application is not performed on the other unselected banks, and current consumption does not occur, thereby contributing to low power consumption.
Also, FIG. 8 of Patent Document 1 depicts an example, where a plurality of above-described banks (memory cell arrays) are disposed in a mask ROM having a memory cell array structure of a general virtual ground type, of a current route when a memory cell in one bank is read and a current route when a pre-charge voltage is supplied to the same bank. A drain in a memory cell transistor of a memory cell of a virtual ground type is connected to a bit line, and its source is connected to a virtual ground line, the bit line and the virtual ground line alternately extending in a column direction. Memory cells adjacent to each other in a row direction across the bit line share the bit line, and memory cells adjacent to each other in a row direction across the virtual ground line share the virtual ground line. The gate of the memory cell transistor is connected to a word line extending in a row direction.
In the multibank scheme depicted in the drawing, the word lines of each bank are configured such that corresponding word lines are connected to each other to be shared by a common word driver, and bank selection is performed with a bit line and a virtual ground line. That is, a main bit line and a main virtual ground line are provided so as to go across each of the banks arranged in a column direction. In each bank, one main bit line is provided for two bit lines, and one main virtual ground line is provided for two virtual ground lines. One main bit line is connected individually to two bit lines via two bank selection transistors with different bank selection lines as gate inputs. Simultaneously, one main virtual ground line is connected individually to two virtual ground lines via two bank selection transistors with different bank selection lines as gate inputs.
In the structure exemplarily depicted in the drawing, for example, in each of the banks BK0 to 3, 32 memory cells in a row direction and 32 memory cells in a column direction are arranged in a matrix. Furthermore, the banks BK0 to 3 are also arranged in a matrix of 2×2. For example, when a memory cell to be read is present in the bank BK0, all of the bank selection transistors connected to the bank BK1 to 3 are turned OFF. With this, no current is supplied to the banks BK1 to 3 except the bank BK0, and reduction in consumed current can be achieved, which is the same as the cross-point memory. In the drawing, to read a memory cell current of the selected memory cell to be read in the bank BK0, which is surrounded by a circle mark in the drawing, one bank selection line is activated to turn one bank selection transistor ON and turn the other bank selection transistor OFF. A solid arrow indicates a memory cell current route. The signal levels of two bank selection lines for bit line selection and for virtual ground line selection are determined when the selected memory cell is read. Thus, a pre-charge voltage is supplied to a bit line three lines away from the selected memory cell to the right in the drawing. The current route to which this pre-charge voltage is supplied is indicated by a broken arrow.
Furthermore, FIG. 1 of Patent Document 1 depicts an example of a multibank scheme in which the number of main data lines GDLm to be connected to each of banks disposed on the same row is half (four) the number (eight) of data lines DLi of each bank. Here, min a main data lines GDLm represents a main data line number. To main data lines GDLm, a data line driver 10 individually driving the lines and supplying a predetermined data line voltage is connected. A data-line selection transistor TDik is disposed between the main data lines and the data lines. The data-line selection transistor TDik is controlled by a bank data selection line SDik connected to its gate. By appropriately controlling the bank data selection line SDik, any one of banks BKk is selected, and either one or both of two data lines DL corresponding to one main data line GDL are selected.